1. Technical Field of the Invention
The present invention relates to avalanche photodiodes.
2. Description of Related Art
The avalanche process in solid-state devices has been known for at least fifty years, as has its application to photo-multiplication. An avalanche is triggered when reverse biasing a PN junction to around the breakdown voltage. This effect can be used in two modes of operation. Commonly, the avalanche photodiodes are biased just below the breakdown voltage, with the photocurrent remaining being proportional to the incoming light intensity. Gain values of a few hundreds are obtained in III-V semiconductors as well as in silicon. This mode of operation has been extensively studied in the literature.
Alternatively, to detect very weak light intensities, the photodiode can be biased above the breakdown voltage in the so-called “Geiger” mode. This mode of operation requires the introduction of a quenching mechanism to stop the avalanche process. Each incoming photon results in a strong current pulse of few nanoseconds duration. The device works as an optical Geiger counter. In this mode of operation the device is known as Single Photon Avalanche Diode (SPAD).
An important technological problem has been to avoid the breakdown at the edge of the p/n junction. In group III-V materials as well as in silicon, specific technologies have been developed for diode fabrication. Usually, a guard ring is introduced to prevent the edge breakdown. These specific steps however are not included in standard CMOS technologies and silicon-SPADs have required costly hybrid electronics.
Single photon counting devices have only recently been successfully integrated in CMOS technologies opening the way to non-PMT based fully solid-state single photon sensing devices.
There are a number of SPAD device structures which can be formed in standard CMOS. The most critical aspect of their construction is the formation of a guard ring to prevent premature edge breakdown. This guard ring is usually made of p-well material, although shallow trench isolation (STI) techniques have also been used. The other type of structure is the “enhancement” or “virtual guard ring” structure.
Such SPADs are sensitive at short wavelengths, which is largely due to the use of shallow source-drain implants to form the avalanche region. SPADs have been created in a variety of CMOS linewidths from 0.8 μm to 0.13 μm. Process variants such as SOI, high voltage and BiCMOS process variants have been employed, making use of additional wells and implants to create suitable guard ring structures and avalanche breakdown regions.
SPADs integrated in 0.8 μm CMOS process in 2000 and more recently in 0.35 μm have shown good photon detection efficiency (PDP) and low dark count, in the region of tens of Hz at room temperature. Diameters of these devices typically range from 5-20 μm. Research is ongoing in the formation of SPADs in 180 nm and 130 nm where a number of groups have presented results. However, the dark count is in the tens of kHz to MHz range rendering these devices of less interest for the majority of photon-starved applications requiring low noise. The dark count mechanism has switched to tunneling in CMOS technologies from the 0.18-μm node onwards. The high doping concentration levels cause a very narrow depletion region resulting in a significant number of tunneling-induced carriers and increased dark count.
In particular, the doping levels of the n-well and p+ (p-diffusion) forming the avalanche breakdown p-n junction are excessively high. Such junctions and wells are required for reasons of efficient PMOS transistor formation in scaled CMOS technologies. However, they are contrary to the requirements for avalanche photodiode operation.
There is therefore no obvious method to form a low-noise SPAD in standard CMOS technologies from the 0.25-μm node onwards as all the known constructions (see, FIG. 1) employ the p+ to n-well junction. Other junctions have been employed recently requiring a specialized high-voltage 0.35-μm CMOS technology with low doped n-well regions.
CMOS processes at the 0.25-μm node and beyond employ shallow trench isolation (STI) which is required to isolate transistors from each other. STI is formed by etching shallow trenches in the semiconductor wafer which are then filled with SiO2 to form insulating walls between devices. However the process is known to induce stress and induce leakage currents in photodiodes or dark count in SPADs. The potential benefit of STI is the ability to integrate devices more densely while still providing a degree of optical and electrical isolation.
A number of SPAD structures have been proposed which employ the STI region as a guard ring. By not requiring a periphery of a lower doped material these structures reduce the width of the lateral depletion region and permit higher fill-factor and active area. However, these devices are affected by higher dark count induced by stress and defects at the STI boundary. In a recently proposed SPAD structure a p-type implant is used to surround the STI to passivate traps and defects resulting in a lower dark count. However these devices are still affected by tunneling in the p-diffusion n-well breakdown region resulting in a high overall noise level.
A structure has also been proposed to distance the STI from the p-plus breakdown region by introducing a poly over active (thin-oxide) periphery to the SPAD. Within the proposed device the guard ring is formed from p-well which is bounded by STI coincident with the poly/active edge. Although functional as a guard ring, tunneling in the p-plus/n-well breakdown region prevents the full-benefit of this guard ring structure from being realized.
Another feature of CMOS process generations beyond 0.25-μm is the presence of a deep n-well implant formed by high-energy ion implantation step before n-well formation. Deep n-well contacted by a ring of n-well is used to completely enclose p-well regions in order to isolate NMOS transistors from the remainder of the substrate. The resulting twin-well process has become an industry standard in recent years to obviate increasing noise-coupling issues in nanometer scale process generations.
Consequently, it would be advantageous to be able to produce a sub-0.25-μm CMOS SPAD with low dark-count characteristics that can be manufactured using existing CMOS manufacturing processes (whether common or field specific), without the need for any special or unique implants, which would add considerable cost and complexity.